RESET
END L

;     ldr r3, =0x48000008 /* Configures /CS0 and /CS1 */
;     ldr r2, =0x0000A5BB /* Generated value */
;     str r2, [r3]
WORD 0x48000008 = 0x0000A5BB
;     ldr r2, [r3] /* the MSC register should be read after it is written */
WORD 0x48000008

;     ldr r3, =0X48000004
;     ldr r2, [r3] /* read MDREFR value */
;     str r2, [r3] /* configure K2DB1 and K2DB2 */
WORD 0X48000004 = 0x03CA4FFF 

;     ldr r1, #0xfff
;     bic r2, r2, r1     /* Clear the low bits
;     orr r2, r2, #0x018 /* configure a valid SDRAM Refresh Interval (DRI) */
;     str r2, [r3] /* store it */
WORD 0X48000004 = 0x03CA4018

;     orr r2, r2, #0x00010000                                 /* assert K1RUN for SDCLK1 */
;     str r2, [r3] /* change from "self-refresh and clock-stop" to "self-refresh" state */
WORD 0X48000004 = 0x03CB4018 

;     bic r2, r2, #0x00400000                                  /* clear SLFRSH bit field */
;     str r2, [r3] /* change from "self-refresh" to "Power-down" state */
WORD 0X48000004 = 0x038B4018 

;     orr r2, r2, #0x00008000                                  /* set the E1PIN bit field */
;     str r2, [r3] /* change from "Power-down" to "PWRDNX" state */
WORD 0X48000004 = 0x038BC018 

;     nop /* no action is required to change from "PWRDNX" to "NOP" state */
;         /* ** Dev Manual sect. 5.14 step 4 -- (Skip if no SDRAM) */
;     ldr r3, =0X48000000 /* Load the SDRAM Configuration register. Must not be enabled yet. */
;     ldr r2, =0x000019C8 /* Generated value */
;     str r2, [r3] /* Write to MDCNFG register */
WORD 0X48000000 = 0x000019C8 

;     wait happens because jtag is slow


;    ldr r3, =0xA0000000 
;     mov r2, #8 /* now must do 8 refresh or CBR commands */
; /*before the first access  */
;CBR_refresh1:
;     nop
;     nop
;     str r2, [r3]
;     nop
;     nop
;     subs r2, r2, #1 
;    bne CBR_refresh1 
;     nop

WORD 0xA0000000 = 0x00000008
WORD 0xA0000000 = 0x00000007
WORD 0xA0000000 = 0x00000006
WORD 0xA0000000 = 0x00000005
WORD 0xA0000000 = 0x00000004
WORD 0xA0000000 = 0x00000003
WORD 0xA0000000 = 0x00000002
WORD 0xA0000000 = 0x00000001
WORD 0xA0000000 = 0x00000000

;    ldr r3, =0X48000000 /* sdram config -- sdram enable */
;    ldr r2, [r3]
;    orr r2, r2, #0x00000001 /* enable appropriate banks, value depends on selected banks */
;    str r2, [r3] /* write to MDCNFG */
WORD 0X48000000 = 0x000019C9 

;    ldr r3, =0x48000040 /* write the MDMRS */
;    ldr r2, =0x00020022 /* the writable bits will be written as a 0 */
;    str r2, [r3] 
WORD 0x48000040 = 0x00020022

;    ldr r3, =0X48000004 /* enable auto-power-down */
;    ldr r2, [r3]
;    orr r2, r2, #0x00100000                                   /* set the APD bit */
;    str r2, [r3] /* write to MDREFR */\
WORD 0X48000004 = 0x039BC018


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PC 0XA3F00000
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